FIG. 1 shows a cross sectional view of a simplified illustration of one example of a conventional pin photo diode 100. The pin photo diode 100 is capable of use in a optoelectric integrated circuit or OEIC (not shown). The OEIC may further include other devices such as a heterojunction bipolar transistor or HBT (not shown), for example.
The pin photo diode 100 is formed on a substrate 110, which may be for example InP. On the substrate 110 is an isolation mesa 120 may be doped with n+ dopant to form a subcollector. Formations of the isolation mesa 120 functions to electrically isolate the photo diode from adjacent devices (not shown) on the OEIC (not shown). To provide electrical connection, collector metal 130 is located on the isolation mesa 120. An intrinsic or lightly doped n− layer 140 is located between the isolation mesa 120 and a base layer 150, which may be doped with p+ dopant. A ring, or partial ring, of base metal 160 provides an opening for light to pass through to the intrinsic layer 140, and provides electrical connection with the base layer 150.
The isolation mesa 120 typically includes n+ type dopant in a semiconductor material, while the base includes a p+ type dopant in semiconductor material. The p type-intrinsic-n type or p-i-n configuration may be fabricated using masking and etching techniques known in the art.
With pin photo diodes 100, as with HBT transistors, base-to-collector capacitance limits the bandwidth of a device. A trade-off exists between series resistance and capacitance of the device. For low series resistance you need a large collector contact 130 and a large base contact 160. A large subcollector (isolation mesa 120)-to-base 150 overlap, however, increases the capacitance of the device. Ideally a low RC time constant is desired. This is particularly desirable in high performance devices operating at high frequency. Thus, what is needed is a device with low capacitance and low resistance.